The invention relates to a method and a circuit for driving at least one voltage controlled power switch device such as a power MOSFET, JFET or an insulated gate bipolar transistor (IGBT). Further, possible power switch devices are thyristors or power Darlington transistors. Power devices such as FET field effect transistors (FETs) or IGBTs are mainly used as switches to convert power from one form to another. Power switch devices can be used in motor controlled systems, uninterrupted power supplies, high-voltage DC transmission and in many other conversion applications.
Pulse width modulation (PWM) is a commonly used technique for controlling power applied to electrical devices by using electronic power switches. An average value of voltage and current fed to the load is controlled by turning the switch on and off at a fast pace. The longer the switch is on compared to the off-periods the higher is the power supplied to the respective load. The duty cycle of the PWM signal indicates a proportion of the on time to the regular interval or period. A low duty cycle corresponds to low power because the applied voltage is off for most of the time. The pulse width modulation switching frequency is faster than the frequency affecting the load, i.e. the device that uses the supplied power. The advantage of such a power supply is that by using pulse width modulation a power loss in the switching device is lower than using conventional power supplies. When a power switch is turned off there is practically no electrical current flowing and when the power switch is turned on there is almost no voltage drop across the power switch. Consequently, the power loss being the product of voltage and current is in both cases close to zero. The pulse width modulation PWM uses a rectangular pulse wave whose pulse width is modulated resulting in the variation of the average value of the waveform.
PDM (Pulse Density Modulation) and PWM (Pulse Width Modulation) are methods for modulating signals where PDM uses a variable carrier frequency and a fixed on-time signal duration and where PWM uses a fixed carrier frequency and a variable on-time signal duration. With a sufficiently high switching frequency and, when necessary, using additional passive electronic filters the pulse train can be smoothed and an average analogue waveform can be recovered. High frequency pulse width modulated power control systems can be realized with semi-conductor switches such as MOSFETS or insufated gate bipolar transistors IGBTs. Because of the availability of fast switching devices and high speed control integrated circuits switching power supplies have become popular. Pulse width modulated converters can employ square wave pulse width modulation to achieve a voltage regulation. The average output voltage is varying the duty cycle of the power switch.
In many converting electronic power switches are often connected as a half bridge. The converting electronic circuit allows a voltage conversion in both directions, i.e. DC voltage between different levels as well as a conversion between DC voltage and AC voltage.
Power switches connected as a half bridge circuit are switched on alternatively. The power loss P for a turned on power switch depends on its inner resistance R and the load current ILoad. Hence, the characteristics of power switches normally show a very low on resistance so that electrical losses are not high (P=ILoad2·R). When the load current ILoad switches from a first power switch to a second power switch an off-state of the first power switch is obligatory to prevent a cross conduction current between the power supply terminals over these power switches. Accordingly, the on switching of the second power switch can only be executed or performed after the first power switch of the half bridge connected power switches has been turned off completely. Accordingly, only one of the two power switches is switched on or turned on at any time to ensure that not both power switches are turned on at the same time. A cross conduction current Icross flowing over both power switches being turned on at the same time would cause a permanent damage to the power switches and a high electro-magnetic interference EMI. Therefore, in order to prevent any possibility that such a situation can occur turning-on of the second power switch must be performed with an additional minor delay, so-called dead time DT, after the first power switch has been turned off. The minimum value of the dead time DT is given by a worst case combination of the driver signal propagation delay and transition time as well as propagation delay and rise time of the power switches under all possible working conditions.
Increasing the dead time DT also increases the reliability of the circuit against cross conduction currents, however it diminishes a switching ratio especially for high switching frequencies and causes distortion especially for class D amplifiers. Furthermore, by increasing the dead time DT the conduction and switching losses are also increased since in the off time of a power switch the electrical current could flow via an integrated diode of the power switch. The integrated diode of the power switch has worse conducting and switching characteristics than the power switch which is switched on.
During a hard switch power losses reach their maximum value when a power switch takes over the current that had flown via a parasitic diode of the other power switch of the half bridge circuit. For the transient time duration a short cut current occurs. Switching time of a parasitic diode is typically in a range from 40 ns to 800 ns so that the switching losses can reach more than 10 mJ per switch. A conventional way of reducing such hard switch losses is mainly the reduction of the working pulse width modulation PWM frequency and reducing the effects of the parasitic diode. The reduction of a working PWM frequency can be useful only for application circuits having a sufficient inductance loads but for an application including also an LC filter the reduced working PWM frequency makes a much bigger LC filter necessary and the response time to power supply and load changes is increased significantly. An ideal hard switch with minimum power losses would theoretically be reached in a case where the dead time DT is zero as an electrical charge on the parasitic diode cannot appear.
A conventional circuit having two half bridge connected power switches PT1, PT2 is shown in FIG. 39. The conventional driving circuit does comprise half bridge connected power switches with a pre-set dead time DT wherein driving signals P and R are applied to the control electrodes of the power switches PT1, PT2 as shown in FIG. 39. The power switches PT1, PT2 of the circuit as shown in FIG. 39 are formed by driving power MOSFETs. By driving the power MOSFETs PT1, PT2 with appropriately delayed signals a simultaneous activation of the power MOSFETs PT1, PT2 is prevented so that no cross conduction Icross current can occur. The pre-set dead time DT has to take into account the worst case situation and the specific characteristics of the power MOSFETs PT1, PT2.
FIG. 40 shows the signal diagrams of the signals for the conventional driving circuit according to the state of the art as shown in FIG. 39. The conventional circuit comprises a logic circuit Log C comprising logical gates and a delay circuit. The logic circuit Log C generates two signals B1, C1 in response to an applied signal A formed by a pulse width modulated PWM signal. As can be seen in FIG. 40 signal B1 is delayed with respect to the other signal C1 generated by the logic circuit Log C. Signals B1, C1 are applied to two different driving circuits DR1, DR2 being connected to a DC/DC converter wherein the driving circuits DR1, DR2 output corresponding driving signals P, R for the two half bridge connected power switches PT1, PT2 as shown in FIG. 39. The power switches PT1, PT2 are formed by MOSFETs being connected to each other at an output terminal OUT to which also a load is connected. As can be seen in FIG. 40 there is a predetermined dead time DT between the time when the driving signal R reaches the threshold voltage of the second power switch PT2 and the time when the driving signal P reaches the threshold voltage of the first power switch PT1. The pre-set dead time DT is in a conventional circuit typically set to at least 100 nsec.
FIG. 41 shows an alternative implementation of a driving circuit according to the state of the art and FIG. 42 shows the corresponding signal diagrams. In the implementation of FIG. 41 no logic circuit having an integrated delay circuit is provided but the dead time DT is generated by means of additional circuitry including a capacitor Cbs as shown in FIG. 41. The conventional driving circuits as shown for example in FIGS. 39, 40 do not allow short dead times DT and cannot switch fast enough especially for high working voltages. The switching voltages of the conventional driving circuits as shown in FIGS. 39, 40 are high and rise fast with rising working PWM frequencies. Consequently, the high switching losses of these conventional driving circuits reduce the efficiency of the whole device.
Generally when driving a power switch device PT such as a MOSFET the switching speed is limited by the fact that the driving current applied to the control electrode or gate of the power switch device is decreased when the voltage of the driving signal reaches the threshold voltage of the power switch device PT.